Purpose
The RT9089A is a sink/source tracking termination regulator. This document explains the function and use of the RT9089A evaluation board (EVB), and provides information to enable operation, modification of the evaluation board and circuit to suit individual requirements.
Introduction
General Product Information
The RT9089A is a sink/source tracking termination regulator. It is specifically designed for low-cost and lowexternal component count systems. The RT9089A possesses a high speed operating amplifier that provides fast load transient response and only requires a minimum 10μF ceramic output capacitor. The RT9089A supports remote sensing functions and all features required to power the DDRI/DDRII/DDRIII and Low Power DDRIII/DDRIV VTT bus termination according to the JEDEC specification. The RT9089A is available in the thermal efficient package, WDFN-10L 2x2.
Product Feature
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VIN Input Voltage Range : 1.1V to 3.5V
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VCNTL Input Voltage Range : 2.9V to 5.5V
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Support Ceramic Capacitors
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10mA Source/Sink Reference Output
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Meet DDRI, DDRII JEDEC Spec
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Support DDRIII, Low Power DDRIII/DDRIV VTT Applications
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Soft-Start Function
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UVLO and OCP Protection
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Thermal Shutdown
Applications
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Notebook/Desktop/Server
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Telecom/Datacom, GSM Base Station, LCD-TV/PDPTV, Copier/Printer, Set-Top Box
Key Performance Summary Table
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Key Features
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Evaluation Board Number : PCB043_V1
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VIN Input Voltage Range
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1.1V to 3.5V
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VCNTL Input Voltage Range
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2.9V to 5.5V
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Max Output Current
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2A
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Default Output Voltage
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Set by VDDQSNS pin voltage level (VOUT = VDDQSNS / 2)
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Default Marking & Package Type
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RT9089AGQW, WDFN-10L 2x2
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Bench Test Setup Conditions
Headers Description and Placement
Please carefully inspect the EVB IC and external components, comparing them to the following Bill of Materials, to ensure that all components are installed and undamaged. If any components are missing or damaged during transportation, please contact the distributor or send e-mail to evb_service@richtek.com
Test Points
The EVB is provided with the test points and pin names listed in the table below.
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Test point/
Pin name
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Signal
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Comment (expected waveforms or voltage levels on test points)
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VIN
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Input voltage
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Power input of the regulator.
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VOUT
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Output voltage
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Power output of the regulator.
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VDDQSNS
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Reference input
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Reference input.
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GND
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Ground
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Analog ground. Connect to negative terminal of the output capacitor. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation.
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PGND
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Power ground
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Power ground of the regulator.
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SENSE
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Voltage sense input
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Voltage sense input for the regulator. Connect to positive terminal of the output capacitor or the load.
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REFOUT
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Reference output
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Reference output. Connect to GND through a 0.1µF ceramic capacitor.
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S3
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S3 signal input
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S3 signal input.
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S5
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S5 signal input
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S5 signal input.
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VCNTL
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Power good output test point
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Control voltage input. Connect this pin to the 3.3V or 5V power supply. A ceramic decoupling capacitor with a value 4.7µF is required.
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Power-up & Measurement Procedure
1. Short J1, J8, the (1, 2) pin of J2 and the (1, 2) pin of J7 by jumper respectively.
2. Provide input voltage (2.9V < VCNTL < 5.5V) to VCNTL pin.
3. Connect input power (1.1V < VIN < 3.5V) and input ground to Vin and GND pins respectively.
4. Connect positive end and negative end of load to VOUT and GND of output pins respectively.
5. The output voltage (VOUT) can be set by the voltage level of VDDQSNS, since VDDQSNS is short with VIN :
VOUT = (VDDQSNS / 2) = (VIN / 2)
Specification
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Parameter
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Symbol
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Min
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Typ.
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Max
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Units
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Control Input Voltage
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VCNTL
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2.9
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5.5
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V
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Supply Input Voltage
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VIN
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1.1
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3.5
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V
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VOUT Source Current Limit
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ILIM_VOUT_SR
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2
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|
A
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VOUT Sink Current Limit
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ILIM_VOUT_SK
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2
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|
A
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Schematic, Bill of Materials & Board Layout
EVB Schematic Diagram
Bill of Materials
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Reference
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Qty
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Part Number
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Description
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Package
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Manufacture
|
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U1
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1
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RT9089AGQW
|
DDR Termination Regulator
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WDFN-10L 2x2
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RICHTEK
|
|
C12
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1
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C2012X5R0J475KT00HW
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4.7µF/6.3V/X5R
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C-0805
|
TDK
|
|
C13
|
1
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0805B104K500
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0.1µF/50V/X7R
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C-0805
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WALSIN
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C2, C3
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2
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C2012X5R1C106KT
|
10µF/16V/X5R
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C-0805
|
TDK
|
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C6
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1
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C2012X5R1C106KT
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10µF/16V/X5R
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C-0805
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TDK
|
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C1, C4, C5, C7, C8, C9, C10, C11, C14, C15, C16, C17, C18, C19, R2, R5
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16
|
|
NC
|
|
|
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R1, R4
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2
|
|
0Ω
|
R-0603
|
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PCB Layout
Top View (1st layer)
PCB Layout—Inner Side (2nd Layer)
PCB Layout—Inner Side (3rd Layer)
Bottom View (4th Layer)